Semiconductor Technology

EDGE SMT
CHIP
PORTFOLIO

EdgeChip E1 vs Apple M4. EdgeChip Zeus vs every AI accelerator on Earth. EdgeChip Exodus — never licensed, never matched, never revealed except in private for a 10-figure conversation. MoS₂ replaces silicon. WATS replaces TSMC. No foreign foundry. No ARM license. No silicon. Ever.

11
Layers — EdgeChip E1
101
Layers — EdgeChip Zeus
10,001
Layers — EdgeChip Exodus
0
Silicon — Any EdgeChip
0
Foreign Foundry Dependency
EdgeChip E1-S
EdgeChip E1-S — Compute Layers (visual reference)
EdgeChip E1-C
EdgeChip E1-C — Bottom Foundation Layer (visual reference)
EdgeChip Zeus
EdgeChip Zeus — 101 Layers
EdgeChip Exodus
EdgeChip Exodus — 10,001 Layers
The Three-Tier Architecture
Every EdgeChip regardless of tier is grown by WATS on a MoS₂ 2D semiconductor substrate with a C-12 diamond / Diaphene base. The architecture is always the same: E1-C is grown first as the bottom foundation layer — the root of trust, the only component treated as inherently trusted. E1-S compute layers then grow on top of it. The chip is one monolithic grown structure. E1-C and E1-S are not two dies bonded together — they are sequential layers of the same continuous WATS fabrication run. The one-way graphene channel between them is a physical property of the grown structure, not a software configuration. E1-S can send requests downward to E1-C. E1-C processes them and returns 124-byte signed packets upward. E1-S never sees the keys. Never touches the enclave. The tier is determined by how many E1-S layers grow above the single E1-C base. E1: 10 E1-S layers. Zeus: 100. Exodus: 10,000. The images on this page show two separate chips for visual reference of the S and C identity — in the actual chip, E1-C is the bottom layer and E1-S layers are everything above it.
EdgeChip E1
Entry Tier
EdgeChip E1
11
MoS₂ layers — E1-S and E1-C variants
The chip that proves WATS works. 30mm × 30mm die. 400 trillion transistors. ~250 million cores. 200 trillion TFLOPS. 25 THz. 2–20 petabytes on-die memory. Zero TDP. E1-C is the bottom security foundation — hardware-isolated, one-way channel, keys never leave. Virtually unlimited compute capability. No silicon. No TSMC. No ARM license.
~250 million cores per chip
2–20 petabytes on-die — no separate DRAM ever
EdgeGPU grown in same WATS run — no separate GPU chip
Sub-1V operation — MoS₂ advantage
E1-C: ML-KEM-1024, ML-DSA-87, SLH-DSA
USPTO #64/060,221
EdgeChip Zeus
Advanced Tier
EdgeChip Zeus
101
MoS₂ layers — never licensed externally
What gets delivered when a partner thinks they're getting E1-C. 101 layers of stacked 2D semiconductor architecture. The performance delta between E1 and Zeus is not incremental — it is categorical. Zeus is what AMD sees when they think the meeting is about E1. Zeus is what starts the bidding war. Zeus recipes are never licensed. Zeus is only built by Edge SMT.
101 grown MoS₂ layers
EdgePhone EP-1 exclusive processor
Zeus-S (system) + Zeus-C (cryptographic)
Never licensed — Edge SMT exclusive
Recipe never leaves Edge SMT
EdgeChip Exodus
Sovereign Tier — Private
EdgeChip Exodus
10,001
MoS₂ layers — one buyer, one price
10,001 layers. Not disclosed publicly. Not benchmarked publicly. Not compared publicly. Exodus exists. It has been built in simulation. It will be revealed exactly once, in a private meeting, to a single buyer, for a 10-figure conversation. This is the only public acknowledgment that Exodus exists. Nothing further will be said about it here.
10,001 grown MoS₂ layers
Revealed only in private — one buyer
10-figure conversation required
Never licensed. Never replicated.
2D Semiconductor Processor
EdgeChip E1

EdgeChip E1 is a MoS₂-fabricated processor grown entirely by the WATS machine. No silicon. No TSMC. No foreign foundry of any kind. The chip architecture runs 11 layers of 2D semiconductor material — each layer grown photochemically at atomic precision, zero defects by design.

The 10 E1-S compute layers deliver ~250 million cores, 200 trillion TFLOPS, and a 25 THz clock across a 30mm × 30mm die containing 400 trillion transistors. On-die memory: 2–20 petabytes. No separate GPU. No separate RAM. No separate storage. One EdgeChip E1. One firmware. ~250 million cores. On-die memory scales with the 400 trillion transistor die — measured in petabytes to exabytes. No separate RAM. No separate GPU. No separate storage. Everything is the chip.

E1-C is not a firmware variant and not a separate chip — it is the bottom grown layer of every EdgeChip E1, the root of trust, unreachable from the E1-S compute layers above it except through a single one-way hardware channel grown into the chip structure. E1-C runs eight post-quantum cryptographic algorithms in hardware — ML-KEM-1024, ML-DSA-87, SLH-DSA, AES-256-GCM, SHA-3-512, BLAKE3, plus two additional. Keys generated in E1-C never leave the E1-C layer. The E1-S layers above are treated as potentially compromised by default. The security is grown in, not configured in.

Sub-1V operation across the full chip means power consumption at a fraction of silicon equivalents. MoS₂ enables transistor operation below the voltage floor that silicon requires — an inherent material advantage that no silicon fab process can engineer around.

USPTO #64/060,221 (EdgeChip E1) · #64/031,539 (EdgeCipher / E1-C)
EdgeChip E1-S — compute variant in optical glass
EdgeChip E1-S — 11-layer MoS₂ compute processor, no silicon
Comparison

EDGECHIP E1
VS LEADING PROCESSORS

Every processor Apple, AMD, Intel, and Qualcomm makes runs on silicon fabricated at TSMC in Taiwan. A single geopolitical event ends that supply chain. EdgeChip E1 has no silicon, no TSMC, and no Taiwan dependency — and it ships with post-quantum cryptography that none of those chips have at all.

Metric EdgeChip E1 Apple M4 Pro AMD EPYC 9654 Qualcomm Snapdragon X Elite
SubstrateMoS₂ — no silicon, no foreign foundrySilicon — TSMC N3B, TaiwanSilicon — TSMC N5, TaiwanSilicon — TSMC N4P, Taiwan
Layers11 grown MoS₂ layers — atomic precisionSingle-layer — planar silicon processSingle-layer — planar silicon processSingle-layer — planar silicon process
CPU Cores48 per chip — 144 in EdgeConsole Titan (3 chips)12 performance + 4 efficiency96 cores per socket12 Oryon cores
Integrated RAM2–20 petabytes on-die — 30mm × 30mm — zero separate DRAM everOn-package HBM — separate processRequires DDR5 — fully separate modulesRequires LPDDR5 — separate modules
Post-QuantumE1-C hardware enclave — 8 algorithms, unbypassableNoneNoneNone
Operating VoltageSub-1V — MoS₂ material advantage~1.0–1.2V — silicon floor~1.8V — high-core-count silicon~0.9–1.1V — silicon floor
Supply ChainFully sovereign — WATS-grown, US onlyTSMC Taiwan — geopolitical riskTSMC Taiwan — geopolitical riskTSMC Taiwan — geopolitical risk
License RequiredNone — sovereign architectureARM license + TSMC process licensex86 architecture licenseARM license + Qualcomm IP
EdgeChip E1-C — cryptographic enclave in optical glass
EdgeChip E1-C — hardware-isolated cryptographic enclave, keys never leave the chip
Post-Quantum Cryptographic Hardware
EdgeCipher / E1-C

EdgeCipher is the cryptographic architecture that runs inside the E1-C chip variant. Eight hardware-implemented algorithms form an unbypassable post-quantum security suite: ML-KEM-1024 (key encapsulation), ML-DSA-87 (digital signature), SLH-DSA (stateless hash-based signature), AES-256-GCM (symmetric encryption), SHA-3-512 (hashing), BLAKE3 (fast hashing), and two additional algorithms. All three NIST post-quantum standards are covered simultaneously in hardware.

The architecture is physically unique: E1-C never connects to E1-S through any software-accessible interface. There is a single one-way hardware channel between them — data flows in one direction only, and only for specifically authorized cryptographic operations. A compromised E1-S operating system cannot access E1-C. A software exploit cannot reach it. A side-channel attack cannot extract keys because the keys never exist outside the E1-C silicon boundary.

Every key generated in E1-C stays in E1-C. Signing happens in hardware. Verification happens in hardware. ML-DSA-87 produces 124-byte signature packets in hardware at line speed. The attack surface is physical only — the chip must be in your hand to be attacked.

NIST FIPS compliant. Ready for deployment in classified environments, financial infrastructure, defense systems, and any application where "post-quantum" cannot mean a software layer that an OS exploit can bypass.

USPTO #64/031,539 (EdgeCipher) · Integrated into every E1-C variant
Comparison

EDGECIPHER / E1-C
VS CRYPTOGRAPHIC SOLUTIONS

Software encryption runs on the same processor that runs your operating system. If the OS is compromised, the encryption is compromised. Hardware security modules exist but add cost, complexity, and still share attack surface with the host system. EdgeCipher eliminates shared attack surface entirely — E1-C is physically isolated at the silicon level.

Metric EdgeCipher / E1-C AES-256 Software HSM Module (Thales, Entrust) Apple Secure Enclave
Attack SurfacePhysical only — hardware isolated, no software pathFull software attack surface — OS exploitablePhysical + software — network interface exposedPhysical + software side-channel risk
Post-QuantumAll 3 NIST standards — ML-KEM-1024, ML-DSA-87, SLH-DSANone — classical only, quantum-vulnerablePartial — add-on modules, not nativeNone — classical ECC only
Key StorageE1-C enclave — keys physically never leave chipRAM / disk — software accessibleHSM secure element — but network connectedSecure element — but same SoC as main CPU
ArchitectureOne-way hardware channel — E1-C never connects to E1-SShared processor with OS — fully exploitableSeparate hardware but software interface requiredSeparate core but shared SoC — side-channel risk
Signing SpeedML-DSA-87 hardware — 124-byte packets at line speedSoftware RSA/ECC — CPU cycles, slowHardware but proprietary — vendor-lockedECC hardware — fast but not post-quantum
NIST ComplianceFIPS compliant — all 3 PQC standardsFIPS for classical — no PQCFIPS compliant — classical + partial PQCNot FIPS compliant
IntegrationSame chip as compute — zero additional hardwareSoftware — no hardware neededSeparate dedicated hardware module — added costIntegrated into Apple SoC only
Memory & Communications
EdgeMemory & EdgeModem

EdgeMemory is a MoS₂/HZO ferroelectric FET non-volatile memory cell grown in the same WATS run as the EdgeChip. 2 nanosecond switching speed — 100,000 times faster than the best NAND flash. 10¹⁰ endurance cycles. Sub-1V operation. Data survives power-off without the volatility of DRAM or the slowness of NAND. It is simultaneously faster than DRAM and non-volatile like storage — a category that does not exist in silicon.

EdgeModem EM-1 integrates 5G NR, WiFi 7, Bluetooth 5.4, and GPS simultaneously on a single MoS₂ die — grown in the same WATS run as EdgeChip. No Qualcomm license. No ARM license. Post-quantum encryption applied at baseband before the RF signal ever leaves the chip. Every bit transmitted by EdgeModem is encrypted in hardware before transmission. No cleartext exists in the signal chain at any point.

USPTO #64/060,215 (EdgeMemory) · #64/060,415 (EdgeModem EM-1)
EdgeChip E1-S — EdgeMemory and EdgeModem grown in same WATS run
EdgeMemory and EdgeModem — grown in the same WATS run as EdgeChip, zero separate fab
Comparison

EDGEMEMORY
VS MEMORY TECHNOLOGY

NAND flash is slow. DRAM is fast but volatile. No existing memory technology is simultaneously fast, non-volatile, high-endurance, and grown on the same substrate as the processor. EdgeMemory is all four simultaneously.

Metric EdgeMemory (FeFET) Best NAND Flash (3D TLC) DRAM (DDR5) Intel Optane (3D XPoint)
Switching Speed2 nanoseconds~100–200 microseconds — 100,000x slower~10–20 nanoseconds — 5–10x slower~10 microseconds — 5,000x slower
Endurance Cycles10¹⁰ cycles~3,000–10,000 cycles — 1,000,000x fewer~10¹⁵ cycles — volatile~10⁶ cycles — discontinued
Non-VolatileYes — data survives power-offYesNo — data lost at power-offYes — but discontinued
Operating VoltageSub-1V3.3V program voltage1.1V — high leakage~1.8V
SubstrateMoS₂ — same WATS run as EdgeChipSilicon — separate NAND fab requiredSilicon — separate DRAM fab requiredSilicon — discontinued (Intel exited)
IntegrationGrown into EdgeChip — zero separate moduleSeparate die, separate package, separate boardSeparate DIMM or package — always externalSeparate module — required special mobo
NO SILICON.
NO TSMC.
NO ARM.

Every chip Apple, AMD, Intel, NVIDIA, and Qualcomm makes depends on TSMC in Taiwan, ARM IP licenses, and silicon wafers. Edge SMT depends on none of those things. WATS grows the chip. MoS₂ replaces silicon. EdgeCipher replaces every cryptographic module ever built. EdgeMemory replaces NAND and DRAM simultaneously. EdgeModem replaces Qualcomm. The entire semiconductor stack — grown from recipe files, domestically, in a machine that fits in a room. The supply chain problem is solved at the materials level.

11
Layers — EdgeChip E1
101
Layers — EdgeChip Zeus
10,001
Layers — EdgeChip Exodus
0
Silicon. Foreign Foundry. ARM License.
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